Field
The present application relates generally to error correction methods and memory devices.
Description of the Related Art
Error correction codes (ECCs) have been used to detect and/or correct errors in data read from memory devices. Examples of such codes include, but are not limited to Bose-Chaudhuri-Hocquenghem (BCH) codes, Hamming codes, and Reed-Solomon (RS) codes. Decoders configured to decode data encoded with such codes (hereinafter referred to as a “codeword”) can be incorporated in, for example, controllers, such as an internal controller of a memory device (e.g., a managed NAND device) and/or an external controller configured to be coupled to a memory device(s), among other apparatuses.
In some memory devices, hard data and/or soft data can be read (e.g., sensed and/or transferred) from the memory cells of the memory devices. Hard data can indicate the detected data state of a memory cell that has been read. For example, hard data can indicate whether such a memory cell was sensed to be in a data state representing a binary value of “1” or a data state representing a binary value of “0” (for the page being read). Meanwhile, soft data can indicate more precisely where within the detected data state the memory cell was sensed. For example, soft data can indicate whether such a memory cell was sensed to be within a first portion, a second portion, or a third portion of the detected data state. Some current state of the art ECC decoders, such as low density parity check (LDPC) code decoders, can take advantage of soft data when decoding a codeword. However, working with soft data has various challenges. For example, it may take longer to sense data including soft data than to sense data including only hard data. As another example, transferring soft data from a memory device through an interface, such as the Open NAND Flash Interface (ONFI), can result in a high throughput penalty as more bits of data are transferred than if only hard data was transferred.
Conventional LDPC decoders run a sufficient number of iterations to correct errors in a codeword. As a result, the LDPC decoder can utilize significant power, since running, for example, two iterations will consume approximately twice as much power as running a single iteration. In applications having extremely tight power budgets, this can prevent or inhibit employing a powerful LDPC decoder. In addition, when the input to the LDPC decoder consists of only hard data, the LDPC decoder may need to run more iterations than it would otherwise need if soft data was also input to the LDPC decoder. Also, a different number of iterations may need to be run depending on the number of errors in the codeword, which can pose a serious problem if the application needs a “sustained throughput” and does not tolerate variations in the throughput.